1. Field of the Invention
The present invention relates generally to taped semiconductor devices. The invention also relates to methods of making taped semiconductor devices. More particularly, the invention relates to a method of making leads on chip (LOC) semiconductor devices with ball grid arrays (BGA).
2. Discussion of the Related Art
A known LOC device is shown in U.S. Pat. No. 5,391,918 (Koyanagi et al.). The Koyanagi device has leads located above a semiconductor chip. The leads are separated from the chip by an insulating layer. The leads are connected by wires to bond pads in the center of the chip. The chip, the leads and the wires are encapsulated in a resin package.
The Koyanagi device has a number of disadvantages. One disadvantage is that the leads can be formed on only one chip at a time. To produce the Koyanagi device, the chip must be singulated from a wafer before the leads are formed. There is a need in the art for an improved method of forming leads on unsingulated chips.
Another disadvantage with the Koyanagi device is that the leads extend laterally beyond the side edges of the chip. The lateral dimensions of the leads are substantially greater than those of the chip. Consequently, the Koyanagi device cannot make efficient use of all of the available space on a printed circuit board.
U.S. Pat. No. 5,218,168 (Mitchell et al.) describes a semiconductor device with metal leads formed in a polyimide film. Solder beads connect the leads to respective die circuits and a lead frame. The beads extend through via holes in the polyimide film. A disadvantage with the Mitchell device is that the leads are not applied to the die circuits until after the circuits are diced out of a wafer. The leads are applied separately to singulated semiconductor chips.
Another disadvantage with the Mitchell device is that the lead frame extends beyond the side edges of the chip. Consequently, the area occupied by the finished device is substantially greater than the area available for circuitry on the chip. Since the periphery of the chip is inside the ends of the leads, the Mitchell device cannot fully utilize space on a printed circuit board.
Another disadvantage with the Mitchell device is that high temperature is used to adhere the polyimide film to the semiconductor chip. The high temperature may cause the film and the chip to expand at different rates, which causes misalignment problems.